Address Bus – ADDRARDADDR and ADDRBWRADDR

Versal ACAP Memory Resources Architecture Manual (AM007)
Document ID
AM007
Release Date
2020-11-24
Revision
1.1 English

The address bus selects the memory cells for read or write. When used as SDP memory, the ADDRA port is the RDADDR, and the ADDRB port is the WRADDR. The data bit width of the port determines the required address bus width for a single RAMB18E5 or RAMB36E5, as shown in the following tables.

Table 1. Port Aspect Ratio for RAMB18E5 (When Used as TDP Memory)
Port Data Width Port Address Width Depth ADDR Bus

DIN Bus

DOUT Bus

DINP Bus

DOUTP Bus
9 11 2,048 [10:0] [7:0] [0]
18 10 1,024 [10:1] [15:0] [1:0]
Table 2. Port Aspect Ratio for RAMB18E5 (When Used as SDP Memory)
Port Data Width (1) Alternate Port Width Port Address Width Depth ADDR Bus

DIN Bus

DOUT Bus

DINP Bus

DOUTP Bus
36 9 11 2,048 [10:0] [7:0] [0]
36 18 10 1,024 [10:1] [15:0] [1:0]
36 36 9 512 [10:2] [31:0] [3:0]
  1. Either the read or write port is a fixed width of x32 or x36.
Table 3. Port Aspect Ratio for RAMB36E5 (When Used as TDP Memory)
Port Data Width Port Address Width Depth ADDR Bus

DIN Bus

DOUT Bus

DINP Bus

DOUTP Bus
9 12 4,096 [11:0] [7:0] [0]
18 11 2,048 [11:1] [15:0] [1:0]
36 10 1,024 [11:2] [31:0] [3:0]
Table 4. Port Aspect Ratio for RAMB36E5 (When Used as SDP Memory)
Port Data Width (1)

Alternate Port

Width

Port Address

Width

 Depth ADDR Bus

DIN Bus

DOUT Bus

DINP Bus

DOUTP Bus
72 9 12 4,096 [11:0] [7:0] [0]
72 18 11 2,048 [11:1] [15:0] [1:0]
72 36 10 1,024 [11:2] [31:0] [3:0]
72 72 9 512 [11:3] [63:0] [7:0]
  1. Either the read or write port is a fixed width of x64 or x72.

For block RAMs used as SDP memories, the port name mapping is listed in the following table. Figure 1 shows the SDP data flow.

Table 5. Port Name Mapping for Block RAMs Used as SDP Memories
RAMB18E5 Used as SDP Memory RAMB36E5 Used as SDP Memory
X36 Mode (Width = 36) X18 Mode (Width ≤ 18) X72 Mode (Width = 72) X36 Mode (Width ≤ 36)
DIN[15:0] = DINADIN[15:0] DIN[15:0] = DINBDIN[15:0] DIN[31:0] = DINADIN[31:0] DIN[31:0] = DINBDIN[31:0]
DINP[1:0] = DINPADIN[1:0] DINP[1:0] = DINPBDINP[1:0] DINP[3:0] = DINPADIN[3:0] DINP[3:0] = DINPBDINP[3:0]
DIN[31:16] = DINBDIN[15:0]   DIN[63:32] = DINBDIN[31:0]  
DINP[3:2] = DINPBDINP[1:0]   DINP[7:4] = DINPBDINP[3:0]  
DOUT[15:0] = DOUTADOUT[15:0] DOUT[15:0] = DOUTADOUT[15:0] DOUT[31:0] = DOUTADOUT[31:0] DOUT[31:0] = DOUTADOUT[31:0]
DOUTP[1:0] = DOUTPADOUTP[1:0] DOUTP[1:0] = DOUTPADOUTP[1:0] DOUTP[3:0] = DOUTPADOUTP[3:0] DOUTP[3:0] = DOUTPADOUTP[3:0]
DOUT[31:16] = DOUTBDOUT[15:0]   DOUT[63:32] = DOUTBDOUT[31:0]  
DOUTP[3:2] = DOUTPBDOUTP[1:0]   DOUTP[7:4] = DOUTPBDOUTP[3:0]