An address collision is when both block RAM ports access the same address location
in the same clock cycle. There are two fundamental clock type setups: common clock and
independent clock. Common (synchronous) clocks are driven by a common clock buffer
driver. All other CLKA and CLKB connections are considered independent (asynchronous)
clocks. The CLOCK_DOMAINS attribute must also be set appropriately. See Table 1 for
legal and default values. If no address collisions are expected or possible (SDP
configurations) to save power, the recommended write mode is NO_CHANGE. Using READ_FIRST
mode has a power penalty over NO_CHANGE and should only be used when necessary for
functionality or to address collision mitigation.
- When both ports are reading, the operations complete successfully.
- When both ports are writing different data, the memory location is written with
non-deterministic data.
- When one port is writing and the other port is reading, the write is
always successful but the resulting read memory value can vary. See the following
tables.
Table 1. Common Clock
| Clock Type |
Write Mode Port A |
Write Mode Port B |
Write Enable Port A (Data) |
Write Enable Port B (Data) |
Resulting Data Out Port A |
Resulting Data Out Port B |
Resulting Memory Value |
| Common |
RF/WF/NC |
RF/WF/NC |
0 |
0 |
Old memory data |
Old memory data |
No change |
| Common |
RF |
RF/WF/NC |
1 (DIA) |
0 |
Old memory data |
Old memory data |
DIA |
| Common |
WF |
RF/WF/NC |
1 (DIA) |
0 |
DIA |
X |
DIA |
| Common |
NC |
RF/WF/NC |
1 (DIA) |
0 |
No change |
X |
DIA |
| Common |
RF/WF/NC |
RF |
0 |
1 (DIB) |
Old memory data |
Old memory data |
DIB |
| Common |
RF/WF/NC |
WF |
0 |
1 (DIB) |
X |
DIB |
DIB |
| Common |
RF/WF/NC |
NC |
0 |
1 (DIB) |
X |
No change |
DIB |
| Common |
RF/WF/NC |
RF/WF/NC |
1 |
1 |
X |
X |
X |
- Common clocked access collision is when the port addresses are
the same for the same clock cycle.
|
Table 2. Independent Clock
| Clock Type |
Write Mode Port A |
Write Mode Port B |
Write Enable Port A (Data) |
Write Enable Port B (Data) |
Resulting Data Out Port A |
Resulting Data Out Port B |
Resulting Memory Value |
| Independent |
RF/WF/NC |
RF/WF/NC |
0 |
0 |
Old memory data |
Old memory data |
No change |
| Independent |
RF |
RF/WF/NC |
1 (DIA) |
0 |
Old memory data |
X |
DIA |
| Independent |
WF |
RF/WF/NC |
1 (DIA) |
0 |
DIA |
X |
DIA |
| Independent |
NC |
RF/WF/NC |
1 (DIA) |
0 |
No change |
X |
DIA |
| Independent |
RF/WF/NC |
RF |
0 |
1 (DIB) |
X |
Old memory data |
DIB |
| Independent |
RF/WF/NC |
WF |
0 |
1 (DIB) |
X |
DIB |
DIB |
| Independent |
RF/WF/NC |
NC |
0 |
1 (DIB) |
X |
No change |
DIB |
| Independent |
RF/WF/NC |
RF/WF/NC |
1 |
1 |
X |
X |
X |
- An independently clocked access collision might occur when the
port addresses are the same and when the clock edges of the two
ports are within the same clock cycle. The UNISIM can report an
error during simulation for collisions when the
SIM_COLLISION_CHECK attribute is set to ALL (default).
|
In Table 1 and Table 2:
- Write enable is active-High, 1 = Write, 0 = Read
- RF = READ_FIRST, WF = WRITE_FIRST, NC = NO_CHANGE
- X = Undeterministic value
- DIA = Port A data input, DIB = Port B data input