Asynchronous/Synchronous Reset Mode Setting - RST_MODE_[A/B]

Versal ACAP Memory Resources Architecture Manual (AM007)

Document ID
AM007
Release Date
2020-11-24
Revision
1.1 English

This attribute determines if the user reset signal is synchronous or asynchronous. By default this is set to synchronous, which means the user can reset the block RAM by using RSTRAM or RSTREG (if output registers are used) to a specified SRVAL. If this attribute is set to asynchronous, ARST_[A|B] resets all pipe stages of the block RAM to 0. The value of the RSTRAM and RSTREG inputs are ignored and not propagated to the block RAM circuit. The SRVAL setting is also ignored.