Each port accesses the same set of 18,432 or 36,864 memory cells using an addressing scheme dependent on whether it is a RAMB18E5 or RAMB36E5. The physical RAM locations addressed for a particular width are determined using these formulae (of interest only when the two ports use different aspect ratios):
END = ((ADDR + 1) × Width) – 1
START = ADDR × Width
The following table shows low-order address mapping for each port width.
| Port Width | Parity Locations | Data Locations | ||||||
|---|---|---|---|---|---|---|---|---|
| 8 + 1 | 3 | 2 | 1 | 0 | Byte3 | Byte2 | Byte1 | Byte0 |
| 16 + 2 | 1 | 0 | Half-Word1 | Half-Word0 | ||||
| 32 + 4 | 0 | Word0 | ||||||