Block RAM Attributes

Versal ACAP Memory Resources Architecture Manual (AM007)

Document ID
AM007
Release Date
2020-11-24
Revision
1.1 English

The following table lists the RAMB18E5 and RAMB36E5 attributes. All attribute code examples are discussed in Block RAM Initialization in VHDL or Verilog Code. Further information on using these attributes is available in Additional RAMB18E5 and RAMB36E5 Primitive Design Considerations.

Table 1. RAMB18E5 and RAMB36E5 Attributes
Attributes Values Default Type Description
BWE_MODE_B PARITY_INTERLEAVED, PARITY_INDEPENDENT PARITY_INTERLEAVED String In PARITY_INTERLEAVED, WEBWE[8] should be connected to 1.
CASCADE_ORDER_A FIRST, MIDDLE, LAST, NONE NONE String Specifies the order of the cascaded block RAMs from the bottom to the top of the chain for port A.
CASCADE_ORDER_B FIRST, MIDDLE, LAST, NONE NONE String Specifies the order of the cascaded block RAMs from the bottom to the top of the chain for port B.
CLOCK_DOMAINS INDEPENDENT, COMMON INDEPENDENT String Either independent clocks connected to port A and B or a single, common clock connected to port A and B.
DOA_REG 0, 1 1 Decimal A value of 1 enables the optional output registers of the RAM port A. Applies to all port A outputs in both TDP and SDP memory usage.
DOB_REG 0, 1 1 Decimal A value of 1 enables the optional output registers of the RAM port B. Applies to all port B outputs in both TDP and SDP memory usage.
RAMB18E5: INIT_00 to INIT_3F

RAMB36E5: INIT_00 to INIT_7F

A 256-bit hex value All 0 Hex Initializes the data content of the block RAM.
RAMB18E5: INITP_00 to INITP_07

RAMB36E5: INITP_00 to INITP_0F

A 256-bit hex value All 0 Hex Initializes the parity content of the block RAM.
READ_WIDTH_A RAMB18E5: 0, 9, 18, 36 (SDP usage)

RAMB36E5: 0, 9, 18, 36, 72 (SDP usage)

RAMB18E5: 0

RAMB36E5: 0

Decimal Specifies the data width for read port A, including parity bits. In SDP mode, this is the read width including parity bits.
READ_WIDTH_B RAMB18E5: 0, 9, 18

RAMB36E5: 0, 9, 18, 36

RAMB18E5: 0

RAMB36E5: 0

Decimal Specifies the data width for read port B including parity bits. Not used for SDP memory usage.
RSTREG_PRIORITY_A RSTREG, REGCE RSTREG String Selects the priority of RESET or CE for the optional output registers. Applies to all port A outputs in both TDP and SDP memory usage.
RSTREG_PRIORITY_B RSTREG, REGCE RSTREG String Selects the priority of RESET or CE for the optional output registers. Applies to all port B outputs in both TDP and SDP memory usage.
RST_MODE_A SYNC, ASYNC SYNC String Determines whether RST_A is synchronous or asynchronous input.
RST_MODE_B SYNC, ASYNC SYNC String Determines whether RST_B is synchronous or asynchronous input.
SLEEP_ASYNC FALSE, TRUE FALSE String Determines if the SLEEP pin is synchronous or asynchronous to the clock.
SRVAL_A RAMB18E5: 18-bit hex value

RAMB36E5: 36-bit hex value

RAMB18E5: 18'h00000000

RAMB36E5: 36'h0000000000000000

Hex Specifies the initialization value of the output latches or register when the synchronous reset (RSTREG) is asserted. Applies to all port A outputs in both TDP and SDP memory usage.
SRVAL_B RAMB18E5: 18-bit hex value

RAMB36E5: 36-bit hex value

RAMB18E5: 18'h00000000

RAMB36E5: 36'h0000000000000000

Hex Specifies the initialization value of the output latches or register when the synchronous reset (RSTREG) is asserted. Applies to all port B outputs in both TDP and SDP memory usage.
WRITE_MODE_A (1) WRITE_FIRST, NO_CHANGE, READ_FIRST NO_CHANGE String Specifies output behavior of write port A. See Write Modes.
WRITE_MODE_B (1) WRITE_FIRST, NO_CHANGE, READ_FIRST NO_CHANGE String Specifies output behavior of write port B. See Write Modes.
WRITE_WIDTH_A RAMB18E5: 0, 9, 18

RAMB36E5: 0, 9, 18, 36

RAMB18E5: 0

RAMB36E5: 0

Decimal Specifies the data width for write port A, including parity bits. When used as SDP memory, this attribute is not valid.
WRITE_WIDTH_B RAMB18E5: 0, 9, 18, 36 (SDP usage)

RAMB36E5: 0, 9, 18, 36, 72 (SDP usage)

RAMB18E5: 0

RAMB36E5: 0

Decimal Specifies the data width for write Port B, including parity bits. In SDP mode, this is the write width including parity bits.
  1. In SDP mode, the WRITE_MODE_A and WRITE_MODE_B must have the same value.