Block RAM attributes and content can be initialized in VHDL or Verilog code for both synthesis and simulation by using generic maps (VHDL) or defparams (Verilog) within the instantiated component. Modifying the values of the generic map or defparam affects both the simulation behavior and the implemented synthesis results. Inferred block RAM can be initialized as well. The Vivado Design Suite templates include the code to instantiate the RAMB primitives, as well as Xilinx Parameterized Macros (XPMs).