In addition to distributed RAM and high-speed SelectIO™ memory interfaces, Versal devices feature a large number of 36 Kb block RAMs. Each 36 Kb block RAM contains two independently controlled 18 Kb RAMs. Block RAMs are placed in columns within the clock regions (CRs) and across the device. A column in a single clock region typically contains 24 block RAMs. The block RAM blocks are cascadable to enable a deeper memory implementation, have a sleep mode for power savings, and have selectable write mode operations. For more information about clock regions, see Versal ACAP Clocking Resources Architecture Manual (AM003).
Note: In some devices, the number of block RAM in the topmost or
bottommost clock region might be reduced by one to accommodate a
boundary logic interface to other blocks. For a sample
description of a boundary logic interface, see
Versal ACAP SelectIO Resources Architecture Manual (AM010).