A block RAM RSTREG in register mode can be used to control the output register as a true pipeline register independent of the block RAM. As shown in the following figure, block RAMs can be read and written independent of register enable or set/reset. In register mode, RSTREG sets DOUT to the SRVAL and data can be read from the block RAM to DBRAM. Data at DBRAM can be clocked out (DOUT) on the next cycle. The timing diagrams in the following figures show different cases of the RSTREG operation.
Figure 1. Block RAM RSTREG in Register Mode
Figure 2. Block RAM Reset Operation in RSTREG Mode
Figure 3. Block RAM Reset Operation in REGCE Mode
Figure 4. Block RAM Reset Operation in Latch Mode
