Applications can build a deep logical SRAM with multiple UltraRAMs. These UltraRAM instances form a matrix such that address, control signals, and input data arrive at the UltraRAM matrix at the bottom left and output data appear at the top right. The following figure illustrates the concept behind the UltraRAM matrix. In this X by Y (row x column) matrix, each matrix element is a single UltraRAM block cascaded vertically. To read/write from/to a matrix, address, control signals and input data (if write) enter the UltraRAM matrix in row 1. A write operation writes the input data to the addressed UltraRAM block at location row, column (R,C) and the word in it. Similarly, for a read operation, the output data reaches the output bus on top of the columns (always) by selecting an UltraRAM R,C and location in it. The figure illustrates a 4x4 UltraRAM matrix.
With the individual address encoding scheme for each UltraRAM, each block individually determines if it should have data. SELF_ADDRESS and SELF_MASK allow for non-unique addresses in a matrix, which allows for the broadcasting of data to multiple UltraRAMs simultaneously in the same cycle. The SELF_ADDRESS can be used as a one-hot encoded address (even partially), and the SELF_MASK determines which address bits are important and which address bits can be ignored (one-cold). Consequently, a global address applied to all UltraRAMs in a matrix can apply to a set of predetermined UltraRAMs. The following figure illustrates a multicast write of data to two, more, or all UltraRAMs in row 1. In this example, the lower four block address bits are ORed via the SELF_ADDR settings for the block that must simultaneously receive data, while the SELF_MASK ignores address bits not to be decoded for a block. In this use case, the UltraRAM can only be used in 1 read/1 write mode.
