The RAMB36E5 in simple dual-port mode can be configured as a single 512 x 64 RAM with built-in Hamming code error correction using the extra eight bits in the 72-bit wide RAM. This operation is transparent.
Eight protection bits (ECCPARITY) are generated during each write operation and stored with the 64-bit data into the memory. These ECCPARITY bits are used during each read operation to correct any single-bit error, or to detect (but not correct) any double-bit error. The ECCPARITY bits are written into the memory.
During each read operation, 72 bits of data (64 bits of data and 8 bits of parity) are read from the memory and fed into the ECC decoder. The ECC decoder generates two status outputs (SBITERR and DBITERR) that are used to indicate the three possible read results: No error, single-bit error corrected, and double-bit error detected. In the standard ECC mode, the read operation does not correct the error in the memory array, it only presents corrected data on DOUT. To improve FMAX, optional registers controlled by the DO_REG attribute are available for data output (DOUT), SBITERR, and DBITERR. This is similar to the optional registers in the block RAM. For further FMAX improvements, an additional ECC pipeline stage is available.
The ECC configuration option is available with a 36 Kb block RAM (RAMB36E5) in simple dual-port mode 72-bit width (64/8) (SDP). Both read and write width must be 72 bits. The RAMB36E5 has the capability to inject errors. The block RAM ECC also supports READ_FIRST, WRITE_FIRST, and NO_CHANGE modes in identical fashion to the SDP usage model.