Built-in Error Detection and Correction

Versal ACAP Memory Resources Architecture Manual (AM007)

Document ID
AM007
Release Date
2020-11-24
Revision
1.1 English

Each UltraRAM 4K x 72 RAM has built in optional Hamming code error correction for each port. The upper (MSB) 8 bits of the 72-bit data bus are used for parity when ECC is turned on. The ECC operation is transparent to the user. All byte write enable BWE[8:0] bits must be set to 1 (High) in ECC mode for proper operation. ECC operations for port A and port B are identical.

Eight protection bits (ECCPARITY) are generated during each write operation and stored with the 64-bit data into the memory. These ECCPARITY bits are used during each read operation to correct any single-bit error, or to detect (but not correct) any double-bit error. ECC data bits and status/control bits are synchronous to the CLK.

During each read operation, 72 bits of data (64 bits of data and 8 bits of parity) are read from the memory and presented to the ECC decoder. The ECC decoder generates two status outputs (SBITERR_A/B and DBITERR_A/B) that are used to indicate the three possible read results: no error, single-bit error corrected, or double-bit error detected. In the standard ECC mode, the read operation does not correct the error in the memory array. It only presents corrected data on DOUT. To improve FMAX, optional registers are available for data output (DO), SBITERR, and DBITERR.

If RST_A/B is asserted, all output registers are reset to 0. Therefore, the SBITERR and DBITERR status signals are also RESET to 0 (Low) indicating that the data output does not have a single bit or a double bit error.

The UltraRAM can also inject errors in either of the ports. ECC mode can inject single bit errors or double bit errors in any or all words. When INJECT_SBITERR is asserted during a write cycle, a single bit error is injected internally in the memory corresponding to DIN[30]. When INJECT_DBITERR is asserted during a write cycle, a double bit error is injected internally in the memory corresponding to DIN[30] and DIN[62]. If both INJECT_SBITERR and INJECT_DBITERR are asserted during a write cycle, a double bit error is injected at the same location as INJECT_DBITERR.

This capability is available in all ECC modes.