Byte-Wide Write Enable

Versal ACAP Memory Resources Architecture Manual (AM007)

Document ID
AM007
Release Date
2020-11-24
Revision
1.1 English

Consider these rules when using the byte-wide write enable feature:

  • For RAMB36E5
    • In x72 SDP mode, WEBWE[8:0] is used to connect the nine WE inputs for the write port. WEA[3:0] is not used. Depending on the BWE_MODE_B the parity bits are either interleaved with the data bits controlled by WEBWE[7:0] or controlled separately by WEBWE[8].
    • In x36 mode, WEA[3:0] is used to connect the four WE inputs for port A and WEBWE[3:0] is used to connect the four WE inputs for port B. WEBWE[7:4] is not used.
    • In x18 mode, WEA[1:0] is used to connect the two user WE inputs for port A and WEBWE[1:0] is used to connect the two WE inputs for port B. WEA[3:2] and WEBWE[7:2] are not used.
    • In x9 or smaller port width mode, WEA[0] is used to connect the single user WE input for port A and WEBWE[0] is used to connect the single WE input for port B. WEA[3:1] and WEBWE[7:1] are not used.
  • For RAMB18E5
    • In x36 SDP mode, WEBWE[3:0] is used to connect the four WE inputs for the write port. WEA[1:0] is not used.
    • In x18 mode, WEA[1:0] is used to connect the two WE inputs for port A and WEBWE[1:0] is used to connect the two WE inputs for port B. WEBWE[3:2] is not used.
    • In x9 or smaller port width mode, WEA[0] is used to connect the single user WE input for port A and WEBWE[0] is used to connect the single WE input for port B. WEA[1] and WEBWE[3:1] are not used.