One of the advanced, built-in features of UltraRAM is the capability to build deeper RAMs by directly cascading UltraRAM blocks in a single column through a dedicated direct interconnect. Ports for data in, data out, ECC error, address, enables, read/write select, and a write mask attribute facilitate cascading (see Figure 1).
Cascading is supported in only one direction and is always in a bottom-up fashion. UltraRAM blocks can be cascade unlimited in a single column within an SLR without limitation and have built-in connections. Cascade pipeline registers (IREG_CAS and OREG_CAS stages are enabled by the REG_CAS attribute) are available options in each UltraRAM. These registers can be enabled as needed depending on the maximum frequency and latency requirements of the design. Cascading from one clock region to the next clock region above can require additional pipeline registers on both the input and output side of the cascade chain to avoid potential setup time violations.
Cascading UltraRAMs across different columns can be achieved using logic and routing resources. The UltraRAM generates a read access status output RDACCESS_A/B to indicate that a read operation was executed. This output has the same latency as the corresponding read data and can be used to determine the correct read data when cascading using multiple columns.
If there is no read operation being performed, the read output at the end of the cascade chain (at the block exit point) will hold the previous data.
UltraRAMs in Versal devices have two cascade options that can be selected by the CASCADE_ORDER attributes to configure the UltraRAMs into cascade chains for control and data flow. There are two CASCADE_ORDER attributes for each port. CASCADE_ORDER_CTRL determines the address, enable, and read/write operations of the blocks in the cascade chain. CASCADE_ORDER_DATA determines the flow of data through the cascade chain. The CASCADE_ORDER_CTRL attribute controls ADDR, EN, and RDB_WR only while the CASCADE_ORDER_DATA attribute controls DIN, BWE, DOUT, RDACCESS, SBITERR, and DBITERR. In most applications the control and data cascades are of identical length. The data cascade can never extend beyond the control cascade chain length in order to avoid read collision. Refer to the following table for all legal combinations of the attributes.
| CASCADE_ORDER_CTRL_A/B | CASCADE_ORDER_DATA_A/B |
|---|---|
| NONE | NONE |
| FIRST | NONE, FIRST |
| MIDDLE | NONE, FIRST, MIDDLE, LAST |
| LAST | NONE, LAST |
Note that the IREG_PRE attribute is used to enable or disable input pipeline registers for inputs that have their corresponding CASCADE_ORDER_CTRL/DATA set to NONE or FIRST. Similarly, the REG_CAS attribute is used to enable or disable cascade pipeline registers when CASCADE_ORDER_CTRL/DATA is MIDDLE or LAST. When CASCADE_ORDER_CTRL and CASCADE_ORDER_DATA are set to different values, both IREG_PRE and REG_CAS attributes can be used to enable pipelines as required. In addition, IREG_PRE can also be used for bit error injection pins that are independent of the CASCADE_ORDER attributes.
The OREG and OREG_ECC pipeline registers must be used identically in a data CASCADE_ORDER. In other words, the above pipeline register must all be either enabled or disabled in a CASCADE_ORDER_DATA chain between the FIRST and LAST UltraRAM block in the data chain.
