Clocking – CLOCK_DOMAINS

Versal ACAP Memory Resources Architecture Manual (AM007)

Document ID
AM007
Release Date
2020-11-24
Revision
1.1 English

This attribute defines if the clocks to ports A and B are independent/asynchronous or common/synchronous. Clocks driven by the same clock source (CLKA and CLKB are connected together) are common. All other CLKA and CLKB connections are independent.