The true dual-port 36 Kb block RAM dual-port memories consist of a 36 Kb storage area and two completely independent access ports, A and B. Similarly, each 18 Kb block RAM dual-port memory consists of an 18 Kb storage area and two completely independent access ports, A and B. The structure is fully symmetrical, and both ports are interchangeable. The following figure illustrates the true dual-port data flow of a RAMB36. The following table lists the port functions and descriptions.
Data can be written to either or both ports and can be read from either or both ports. Each write operation is synchronous, and each port has its own address, data in, data out, clock, clock enable, and write enable. The read and write operations are synchronous and require a clock edge.
There is no dedicated monitor to arbitrate the effect of identical addresses on both ports.
| Port Function | Description |
|---|---|
| ARST_[A|B] | Asynchronous reset that resets the output register for port A and B to all zeros. |
| DIN[A|B] | Data input bus. |
| DINP[A|B](1) | Data input parity bus. Can be used for additional data inputs. |
| ADDR[A|B] | Address bus. |
| WE[A|B] | Byte-wide write enable. |
| EN[A|B] | When inactive, no data is written to the block RAM and the output bus remains in its previous state. |
| RSTREG[A|B] | Synchronous set/reset of the output registers (DO_REG = 1). The RSTREG_PRIORITY attribute determines the priority over REGCE. |
| RSTRAM[A|B] | Synchronous set/reset of the output data latches. |
| CLK[A|B] | Clock input. |
| DOUT[A|B] | Data output bus. |
| DOUTP[A|B](1) | Data output parity bus. Can be used for additional data outputs. |
| REGCE[A|B] | Output register clock enable. |
| CASDIN[A|B] | Cascade data input bus. |
| CASDINP[A|B] | Cascade parity input bus. |
| CASDOUT[A|B] | Cascade data output bus. |
| CASDOUTP[A|B] | Cascade parity output bus. |
| SLEEP | Dynamic shutdown power saving. If SLEEP is active, the block is in power saving mode. |
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