Memories and FIFOs in the programmable logic can be constructed with block RAMs within the Vivado IP integrator block design flow, block RAMs can be inferred during high-level synthesis or synthesis of VHDL or Verilog code, or block RAMs can be explicitly instantiated and initialized in VHDL or Verilog code.
Single- or dual-port memories can be constructed with UltraRAMs that are instantiated and initialized to user-defined values in VHDL or Verilog code. UltraRAMs can also be inferred during synthesis from VHDL or Verilog code. See the Vivado Design Suite User Guide: Synthesis (UG901) for RAM HDL coding techniques.