ECC Modes

Versal ACAP Memory Resources Architecture Manual (AM007)

Document ID
AM007
Release Date
2020-11-24
Revision
1.1 English

In the standard ECC mode (EN_ECC_RD = TRUE and EN_ECC_WR = TRUE), both encoder and decoder are enabled. During write, 64-bit data and 8-bit ECC generated parity are stored in the array. The external parity input bits are ignored. During read, the 72-bit decoded data and parity are read out.

The most common use case is to enable both the ECC encoder and decoder in a port. However, the encoder and decoder can be enabled separately. To enable only the encoder, the data must be sent through the DI port, the ECCPARITY bits are written into the RAM, and the decoder is disabled. To use only the decoder, the encoder is disabled, the data is written into the RAM, and the corrected data and status bits are read out of the UltraRAM.