Important: The clock minimum pulse
width and setup/hold time of the block RAM address, block enable, and write enable pins
must not be violated. Violating the clock minimum pulse width or these setup/hold times
(even if write enable is Low) can corrupt the data contents of the block RAM. This most
commonly occurs during an unstable clock (for example, when unplugging an external clock
source) or when flip-flops driving block RAM control pins are asynchronously reset, such
as a system-wide reset. To avoid this issue, design with synchronous resets only for
both assertion and deassertion. When the clock is not stable, disable the clock buffer
or the logic driving the block RAM control pins, or deassert the block RAM EN
input.