Important: The clock minimum
pulse width and setup/hold time of the UltraRAM address, enable, and sleep pins must not
be violated. Violating the clock minimum pulse width or these setup/hold times (even if
write enable is Low) can corrupt the data contents of the UltraRAM. This most commonly
occurs during an unstable clock (for example, when unplugging an external clock source)
or when flip-flops driving block RAM control pins are asynchronously reset, such as a
system-wide reset. To avoid this issue, ensure stable clocks and design with synchronous
resets for both assertion and deassertion. When the clock is not stable, disable the
clock buffer or logic driving the UltraRAM control pins, or deassert the UltraRAM EN
input.