Navigating Content by Design Process

Xilinx® documentation is organized around a set of standard design processes to help you find relevant content for your current development task. This document covers the following design processes:

System and Solution Planning

Identifying the components, performance, I/O, and data transfer requirements at a system level. Includes application mapping for the solution to PS, PL, and AI Engine. Topics in this document that apply to this design process include:

• Block RAM Introduction
• Synchronous Dual-Port and Single-Port RAMs
• Additional Block RAM Features
• UltraRAM Introduction
• UltraRAM Key Features
• UltraRAM Cascade
• Block RAM and UltraRAM Differences
• Additional Memory Resources

Hardware, IP, and Platform Development​

Creating the PL IP blocks for the hardware platform, creating PL kernels, subsystem functional simulation, and evaluating the Vivado® timing, resource use, and power closure. Also involves developing the hardware platform for system integration. Topics in this document that apply to this design process include:

• Design Entry Methods
• Differences from Previous Generations
• Block RAM Library Primitives
• Additional RAMB18E5 and RAMB36E5 Primitive Design Considerations
• UltraRAM Primitives
• Additional URAM288E5 Primitive Design Considerations
• UltraRAM Timing Diagrams