No Cascade Ports

Versal ACAP Memory Resources Architecture Manual (AM007)

Document ID
AM007
Release Date
2020-11-24
Revision
1.1 English

The following table lists the UltraRAM no cascade ports.

Table 1. No Cascade Ports
Port Name Description
CLK UltraRAM clock source.
SLEEP Dynamic power gating control.
Port A Inputs
ADDR_A[25:0] Port A address. ADDR_A[25:15] are only used in cascade mode.
EN_A Port A enable. Enables or disables the read/write access to the block RAM memory core.
RDB_WR_A Port A read or write mode input select. Read (BAR) is active-Low (0 = read and 1 = write).
BWE_A[8:0] Port A byte write enable.
DIN_A[71:0] Port A write data in.
INJECT_SBITERR_A Port A single-bit error injection during write.
INJECT_DBITERR_A Port A double-bit error injection during write.
OREG_CE_A Port A SRAM array core block read output pipeline register CLK enable.
OREG_ECC_CE_A Port A ECC decoder output pipeline register CLK enable.
RST_A Asynchronous or synchronous reset for port A output registers. Reset has priority over CE.
Port A Outputs
DOUT_A[71:0] Port A read data out.
RDACCESS_A Port A read status output.
SBITERR_A Port A single-bit error output status.
DBITERR_A Port A double-bit error output status.
Port B Inputs
ADDR_B[25:0] Port B address. ADDR_B[25:15] are only used in cascade mode.
EN_B Port B enable. Enables or disables the read/write access to the block RAM memory core.
BWE_B[8:0] Port B byte write enable.
DIN_B[71:0] Port B write data in.
INJECT_SBITERR_B Port B single-bit error injection during write.
INJECT_DBITERR_B Port B double-bit error injection during write.
OREG_CE_B Port B SRAM array core block read output pipeline register CLK enable.
OREG_ECC_CE_B Port B ECC decoder output pipeline register CLK enable.
RST_B Asynchronous or synchronous reset for port B output registers. Reset has priority over CE.
Port B Outputs
DOUT_B[71:0] Port B read data out.
RDACCESS_B Port B read status output.
SBITERR_B Port B single-bit error output status.
DBITERR_B Port B double-bit error output status.