Determines if both cascade data/controls/address inputs and outputs have their pipeline registers (IREG_CAS and OREG_CAS) enabled or not. These pipeline stages play a critical role in determining the maximum frequency of the UltraRAM. In cascade mode, these registers should be used in each block or every few blocks depending on the maximum frequency requirement. IREG_PRE and REG_CAS are mutually exclusive except when the CASCADE_ORDER attribute is set to MIDDLE or LAST, the IREG_PRE register can still be used in the cascade case for the error injection inputs INJECT_S/DBITERR. For all other inputs REG_CAS must be used. See Figure 1.