The optional data, address, and control input registers (IREG_PRE registers) improve design performance by eliminating the routing delay from the CLB flip-flops for pipelined operation. Optional input registers (IREG_CAS registers) for cascading data, address and control are available. Either the data input or the cascade input registers can be used at any given time for an UltraRAM block depending on its configuration (input cascaded or not). Both the input and output cascade registers are enabled via the REG_CAS attribute simultaneously and cannot be turned on or off individually.