Optional Output Register On/Off Switch – DOUT[A|B]_REG

Versal ACAP Memory Resources Architecture Manual (AM007)

Document ID
AM007
Release Date
2020-11-24
Revision
1.1 English

This attribute sets the optional pipeline registers at the A/B output of the block RAM improving the clock-to-out timing. If turned on, this adds an extra cycle of read latency. When turned off, the block RAM data is read in the same clock cycle, however with a slower clock-to-out. The valid values are 0 (default) or 1.