The optional output registers improve design performance by eliminating the routing delay to the CLB flip-flops for pipelined operation. The first optional output register (OREG stage) is immediately after the SRAM array read operation. Additional optional output registers after the ECC decode logic (OREG_ECC stage) and cascade logic (OREG_CAS register) are available. By default, the design uses internally generated CE to control all the pipeline stages for power saving. However, an external CE port can be used by setting the USE_EXT_CE_A/B attribute. When the external CE is enabled, an independent clock enable input port is provided for these output registers. If the output data registers are disabled via their CE port, they hold their value independent of the input register operation.