Power Gating Enable Input – SLEEP

Versal ACAP Memory Resources Architecture Manual (AM007)

Document ID
AM007
Release Date
2020-11-24
Revision
1.1 English

The dynamic power gating capability can be used to save static power when the memory is not actively used for extended periods of time.

When sleep mode is asserted, and setup and hold times are met, the memory starts going into sleep mode in the next clock cycle. The SLEEP inputs disable the UltraRAM read and write operation. Consequently, if a read or write operation is attempted, it is ignored until after the wake-up time is satisfied. However, setup and hold times must be met. While in sleep mode, the output of the SRAM array and the OREG pipeline registers are synchronously reset to 0 with the next rising edge of clock. The other optional pipeline registers are not affected by the sleep mode. Therefore, the ultimate data output value of the UltraRAM is either held at its previous value or appears to be reset to 0 depending on the usage of the other pipeline registers. The output of the OREG register is held to 0 until the first valid read data (after wake-up time) flows through the pipeline.

The SLEEP pin controls the power gating of the RAM. When SLEEP = 1, the SRAM peripheral logic is powered down to save energy. The data in the SRAM array is retained but it cannot be read from or written to. SLEEP allows a two clock cycles wake-up time with no impact on SEU performance. The polarity of this pin is not configurable (active-High).

Wake-up time defines when the EN pin can be asserted after SLEEP has been deasserted. The clock wake-up cycles mentioned previously assume no optional pipelines are enabled.

Note: If the OREG is used (OREG=TRUE) and a read operation is followed immediately by a SLEEP operation (SLEEP going active), the read operation data does not exit the UltraRAM block because the OREG pipeline stage is powered down immediately and RDACCESS does not assert.