The waveforms in the figures are for a three UltraRAM cascade case and assume OREG and OREG_ECC is set to TRUE for all three UltraRAMs in the cascade chain:
- RST input is simultaneously asserted or deasserted at input of all three UltraRAMs.
- All other inputs are driven at input of first UltraRAM. All outputs exit from last UltraRAM.
Note: The DOUT output behavior
after reset might be different depending on the location of
REG_CAS, as shown in the figures.
Figure 1. Reading from Middle UltraRAM – Middle
UltraRAM with REG_CAS=TRUE
Figure 2. Reading from Middle UltraRAM – Last
UltraRAM with REG_CAS=TRUE
