The UltraRAM generates a read access status output (RDACCESS_A/B) to indicate that a read operation finished executing, indicating when new data is available at the output. This output has the same latency as the corresponding read data. This output can then be used at the top level to select the correct read data when cascading UltraRAMs across multiple columns. When this output is High, it indicates a read operation has been executed in that UltraRAM or in an UltraRAM below it that is part of the cascade chain. When crossing columns of cascaded UltraRAMs, CLB registers might be required to account for pipelining in the column cascade.
The main purpose of the RDACCESS signal is to support UltraRAMs that are arranged in a matrix fashion. It identifies which UltraRAM block in a matrix configuration is actively reading data in a given clock cycle. The application can then determine the appropriate read data that needs to be propagated to the final output for processing.
The following figure illustrates a use case where the RDACCESS signal is used to select the correct read output data and control the output data path of a matrix. The circuit holds the data for the inactive outputs. It is important to match the input delay between the matrix entry point (for example, horizontal pipelining in the fabric for performance reasons) with identical delays on the output side (the delay/pipeline blocks shown in the figure).
