Read/Write Waveforms With Reset – With and Without Optional Output Pipeline Registers

Versal ACAP Memory Resources Architecture Manual (AM007)

Document ID
AM007
Release Date
2020-11-24
Revision
1.1 English

The following figures show the read/write waveforms with reset and with and without optional pipeline registers.

Note: Reset has priority over the read operation and reset has no impact on any write operation.
Figure 1. Reset/Read/Write with Attributes RST_MODE=SYNC, IREG_PRE_A/B=FALSE, OREG_A/B=FALSE, OREG_ECC_A/B=FALSE, USE_EXT_CE_A/B=FALSE

Figure 2. Reset/Read/Write with Attributes RST_MODE=SYNC, IREG_PRE_A/B=FALSE, OREG_A/B=TRUE, OREG_ECC_A/B=TRUE, USE_EXT_CE_A/B=FALSE

Figure 3. Read/Write with Attributes RST_MODE=ASYNC, IREG_PRE_A/B=FALSE, OREG_A/B=TRUE, OREG_ECC_A/B=TRUE, USE_EXT_CE_A/B=FALSE