Read/Write Waveforms With and Without Optional Pipeline Registers

Versal ACAP Memory Resources Architecture Manual (AM007)

Document ID
AM007
Release Date
2020-11-24
Revision
1.1 English

The following figures show the read/write waveforms with and without optional pipeline registers.

Figure 1. Read/Write with Attributes IREG_PRE_A/B=FALSE, OREG_A/B=FALSE, OREG_ECC_A/B=FALSE, USE_EXT_CE_A/B=FALSE

Figure 2. Read/Write with Attributes IREG_PRE_A/B=TRUE, OREG_A/B=TRUE, OREG_ECC_A/B=TRUE, USE_EXT_CE_A/B=FALSE