There are two modes for the reset operation. The synchronous and asynchronous reset modes are controlled by the RST_MODE_A/B attributes. In synchronous reset mode, which is the default, all output flip-flops and latches are synchronously reset to 0. In the asynchronous reset mode, all output flip-flops and latches are reset to 0 without waiting for a CLK edge. This operation does not affect UltraRAM memory cells and does not disturb write operations on either of the ports. The polarity for both signals is configurable (active-High by default).
When used in an UltraRAM matrix, the RST input is expected to be asserted (and deasserted) simultaneously at the input of all UltraRAMs in the matrix (in both SYNC and ASYNC reset modes). Consequently, after a RST operation, a new read data is available after N cycles (where N is the read latency of the matrix). However, if the read operation overlaps with the reset operation, the DOUT could change from the reset value to a new read value earlier than the N cycles. This occurs because the read output corresponding to read during or before reset might propagate to the output (because input pipelines IREG_PRE/IREG_CAS are not impacted by the reset). Consequently, this behavior also depends on the REG_CAS locations in the matrix. When the REG_CAS location changes, the DOUT behavior after reset can be different. See the figures in Read/Write Waveforms With Reset – With and Without Optional Output Pipeline Registers for the timing diagrams showing an example of this difference in behavior.