The following table shows the revision history for this document.
| Section | Revision Summary |
|---|---|
| 11/24/2020 Version 1.1 | |
| Block RAM Introduction | Added count of block RAM in a clock region and a note for an exception to the count of block RAM. |
| UltraRAM Introduction | Added a note for an exception to the count of UltraRAM. |
| Power Gating Enable Input – SLEEP | Corrected description of RDACCESS behavior when read is immediately followed by a SLEEP operation. |
| Address Bus – ADDR_A, ADDR_B | Updated description of UltraRAM address bits and added Table 1. |
| Table 1 | Updated description of BWE_MODE. |
| Byte Write Enable Mode – BWE_MODE_[A|B] | Rewrote for clarity. |
| Table 1 | Swapped order of read/write port descriptions in UltraRAM Port Access column. |
| Using ECC Decode Only to Inject Single-Bit Error | Updated description of detected single-bit error types. |
| Using the ECC Decode Only to Inject Double-Bit Error | Updated description of detected double-bit error types. |
| 07/16/2020 Version 1.0 | |
| Initial release. | N/A |