The SLEEP pin provides a dynamic power gating capability for periods when the block RAM is not actively used for an extended period of time. While SLEEP is active (High) the EN pins on both ports must be held Low. The data content of the memory is preserved during this mode. There is a wake-up time requirement of two clock cycles regardless of the SLEEP_ASYNC mode setting. Any block RAM access prior to the wake-up time requirement is not guaranteed and might cause memory content corruption. The attribute SLEEP_ASYNC determines the behavior of this pin with respect to the clocks.