RSTREGARSTREG, RSTREGB, RSTRAMARSTRAM, RSTRAMB, and ARST
In latch mode, the RSTRAM pin synchronously forces the data output latches to contain the value SRVAL. When the optional output registers are enabled (DO_REG = 1), the RSTREG signal synchronously forces the data output registers containing the SRVAL value. The priority of RSTREG over REGCE is determined using the RSTREG_PRIORITY attribute. The data output latches or output registers are synchronously asserted to 0 or 1, including the parity bit. Each port has an independent SRVAL[A|B] attribute of 36 bits. This operation does not affect RAM memory cells and does not disturb write operations on the other port. The polarity for both signals is configurable (active-High by default). When used as SDP memory, the RSTREGA port is the RSTREG, and the RSTRAMA port is the RSTRAM.
ARST_A and ARST_B are asynchronous resets for port A and port B which reset port A and port B outputs to all zeros, respectively. If asynchronous mode is enabled, the output of all pipeline stages is asynchronously set to 0 when ARST is asserted. This is regardless of the block RAM being enabled or the setting of the SRVAL value. Latch mode, register mode, and eccpipe mode are affected by the asynchronous reset. Toggling the synchronous reset pins while in the asynchronous reset mode has no impact on the outputs. All block RAMs in a cascade chain must be driven by the same synchronized input signal.