Each 18 Kb block and 36 Kb block can also be configured in a SDP RAM mode. In this mode, the block RAM port width doubles to 36 bits for the 18 Kb block RAM and 72 bits for the 36 Kb block RAM. When the block RAM is used as SDP memory, independent read and write operations can occur simultaneously, where port A is designated as the read port and port B as the write port. When the read and write port access the same data location at the same time, it is treated as a collision, identical to the port collision in true dual-port mode. Versal devices support these modes when the block RAM is used as SDP memory (READ_FIRST, WRITE_FIRST, NO_CHANGE).
The following figure shows the simple dual-port data flow for RAMB36 when the block RAM is used as SDP memory.
This table lists the simple dual-port functions and descriptions.
| Port Function | Description |
|---|---|
| ARST_B | Asynchronous reset that resets the output register DOUT to all zeros. |
| DOUT | Data output bus. |
| DOUTP | Data output parity bus. |
| DIN | Data input bus. |
| DINP | Data input parity bus. |
| RDADDR | Read data address bus. |
| RDCLK | Read data clock. |
| RDEN | Read port enable. |
| REGCE | Output register clock enable. |
| RSTREG | Synchronous set/reset of the output registers. |
| RSTRAM | Synchronous set/reset of the output data latches. |
| WRADDR | Write data address bus. |
| WRCLK | Write data clock. |
| WREN | Write port enable. |
| SLEEP | Dynamic shutdown power saving. If Sleep is High, the block is in power-saving mode. |
| CASDIN[A|B] | Cascade data input bus. |
| CASDINP[A|B] | Cascade parity input bus. |
| CASDOUT[A|B] | Cascade data output bus. |
| CASDOUTP[A|B] | Cascade parity output bus. |
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