Sleep Waveforms

Versal ACAP Memory Resources Architecture Manual (AM007)

Document ID
AM007
Release Date
2020-11-24
Revision
1.1 English

Sleep has priority over EN. Any attempted memory writes are ignored and the previous memory content is preserved. Any attempted memory reads are also ignored. See the following figures.

Figure 1. Sleep Mode for Write Operations With Attribute IREG_PRE_A/B=FALSE

Figure 2. Sleep Mode for Read Operations With Attributes IREG_PRE_A/B=FALSE, OREG_A/B= FALSE, OREG_ECC_A/B= FALSE, USE_EXT_CE_A/B= FALSE, DOUT is Forced to "0"

Figure 3. Sleep Mode for Read operations With Attributes IREG_PRE_A/B=FALSE, OREG_A/B= FALSE, OREG_ECC_A/B= TRUE, USE_EXT_CE_A/B= FALSE, DOUT is Preserved With Previous Read Data

Figure 4. Sleep Mode For Read Operations With Attributes IREG_PRE_A/B=FALSE, OREG_A/B= TRUE, OREG_ECC_A/B= FALSE, USE_EXT_CE_A/B= FALSE

Figure 5. Sleep Mode for Read Operations With Attributes IREG_PRE_A/B=FALSE, OREG_A/B= TRUE, OREG_ECC_A/B= TRUE, USE_EXT_CE_A/B= FALSE

Read outputs D2, D11, and D19 are lost due to sleep cycle immediately after read (when OREG=TRUE). Consequently, DOUT is driven to "0". However, the RDACCESS is asserted because the internal read memory access is not blocked.

When OREG=TRUE, the read corresponding to address A2 internally is not blocked (because sleep is still Low in this cycle). However, because sleep goes High in the next cycle, the OREG has lost the data, and the output of OREG becomes "0". In this case, even though OREG_ECC=TRUE, because the read itself was not blocked, the OREG_ECC becomes "0" because new read data is expected. This occurs if there is a read operation followed immediately by sleep with OREG=TRUE (irrespective of whether OREG_ECC is TRUE or FALSE).