During read operation, the 72-bit memory content, consisting of 64 bits of data and 8 bits of parity is read out from an address location and decoded internally. If there is no error, the original data and parity are output at DOUT[71:0]. If there is a single-bit error in either the data or the parity, the error is corrected, and SBITERR is High. If there is a double-bit error in the data and parity, the error is not corrected. The original data and parity is output and DBITERR is High.
The OREG optional pipeline stage is available just before the ECC decode logic and the OREG_ECC optional pipeline stage is available just after the ECC decode logic for all the DOUT and error bit outputs. Either or both of these stages can be enabled depending on the maximum frequency and latency requirements of the design.