The ECC encoder uses DIN[63:0] to generate the corresponding 8 bits of ECC parity, appends it to the 64 data bits, and then writes into the memory. Because ECC parity is generated internally, the DIN[71:64] pins are not used.
The IREG_PRE optional pipeline stage is available before the ECC encode logic for all input pins. This stage can be enabled as needed to meet the maximum frequency requirement.