UltraRAM Cascade

Versal ACAP Memory Resources Architecture Manual (AM007)

Document ID
AM007
Release Date
2020-11-24
Revision
1.1 English

The UltraRAM cascade features are:

  • UltraRAM has dedicated routing resources for most of the inputs and outputs to cascade from lower UltraRAM to upper UltraRAM.
  • Built-in address decode logic for 11 bits of the MSB address is used when cascading UltraRAMs to automatically generate internal enable for the read and write operations.
  • Cascading in a column is supported in one direction from bottom to top and can be implemented without using general interconnect resources.
  • Cascading between columns requires the use of device routing and potentially logic resources at the entry and exit points of each column.