UltraRAM blocks are 288 Kb, single-clock, synchronous memory blocks arranged in one or more columns in the device. There are typically 24 UltraRAM blocks per clock region per column. Multiple UltraRAM blocks can be cascaded together within a column using dedicated cascade routing, and the only limit is the height of the device or a single super logic region (SLR) in a stacked silicon interconnect (SSI) device. In addition, multiple columns can be cascaded together using a small quantity of logic resources. There is no timing penalty with cascading UltraRAM blocks if they are appropriately pipelined.
UltraRAM is a flexible, high-density memory building block. Each UltraRAM block can store up to 288K bits of data and is configured as a 4K x 72 memory block. UltraRAM has eight times the capacity of a block RAM. Similar to the block RAM, there are multiple UltraRAM columns distributed on the device. UltraRAM has two ports, both of which address all 4K x 72 bits. Each port can independently perform either one read or one write operation per clock cycle per port. However, internally the SRAM array uses single port memory cells. Dual port operation is achieved by executing port A operation followed by port B operation in a single cycle. Therefore, both ports share a single clock input. Each port can only execute either a write or read operation in one cycle. When executing a write operation, the read outputs are unchanged and hold the previous value.
The 288 Kb blocks can be cascaded to facilitate deeper memory implementations. Most of the routing related to cascading is contained inside the UltraRAM columns. Therefore, very little or no general interconnect is required and timing penalties are not incurred due to routing if the UltraRAM blocks are appropriately pipelined.
UltraRAM contains up to four pipeline stages for each of the two port interfaces. In a standalone, non-cascaded mode, the UltraRAM can be configured for one to four clock cycles latency, though typically, only one to three cycles of latency are required, depending on the target frequency. Cascade mode latency is a function of the size of the UltraRAM chain, frequency target, and other constraints. Similarly, clock-to-out performance depends on the selected output registers. Use the Vivado® tools to determine the performance and clock-to-out timing for specific design implementations.