Revision History
Overview
Introduction to Versal ACAP
Navigating Content by Design Process
Block RAM
Block RAM Introduction
Block RAM Summary
UltraRAM
UltraRAM Introduction
UltraRAM Summary
Additional Memory Resources
Differences from Previous Generations
Block RAM
UltraRAM Block
Design Entry Methods
Block RAM Resources
Synchronous Dual-Port and Single-Port RAMs
Data Flow
Read Operation
Write Operation
Write Modes
WRITE_FIRST or Transparent Mode
READ_FIRST or Read-Before-Write Mode
NO_CHANGE Mode (DEFAULT)
Address Collision
Additional Block RAM Features
Optional Output Registers
Independent Read and Write Port Width Selection
Simple Dual-Port Block RAM
Cascadable Block RAM
Standard Data Output Cascade Mode
Data Out Cascade in Pipeline Mode
Byte-Wide Write Enable
Block RAM Error Correction Code
Power Gating of Unused Block RAMs
Block RAM Library Primitives
Block RAM Port Signals
Clock – CLKARDCLK and CLKBWRCLK
Enable – ENARDEN and ENBWREN
Byte-Wide Write Enable – WEA and WEBWE
Register Enable – REGCEAREGCE and REGCEB
Set/Reset
Address Bus – ADDRARDADDR and ADDRBWRADDR
Data-In Buses – DINADIN, DINPADINP, DINBDIN, and DINPBDINP
Data-Out Buses – DOUTADOUT, DOUTPADOUTP, DOUTBDOUT, and DOUTPBDOUTP
CASDINA
CASDINB
CASDINPA
CASDINPB
CASDOUTA
CASDOUTB
CASDOUTPA
CASDOUTPB
Cascade Selection – CASOREGIMUX
Cascade Selection – CASOREGIMUXEN
Cascade Selection – CASDOMUX
Cascade Selection – CASDOMUXEN
SLEEP
Inverting Control Pins
RAMB18/36 Unused Inputs
Block RAM Address Mapping
Block RAM Attributes
Data Cascading – CASCADE_ORDER
Clocking – CLOCK_DOMAINS
Content Initialization – INIT_xx
Content Initialization – INITP_xx
Read Width – READ_WIDTH_[A|B]
Reset or CE Priority – RSTREG_PRIORITY_[A|B]
Asynchronous/Synchronous Reset Mode Setting - RST_MODE_[A/B]
Power Saving – SLEEP_ASYNC
Output Latches/Registers Synchronous Set/Reset (SRVAL_[A|B])
Optional Output Register On/Off Switch – DOUT[A|B]_REG
Write Width – WRITE_WIDTH_[A|B]
Write Mode – WRITE_MODE_[A|B]
SIM_COLLISION_CHECK
INIT_FILE
Block RAM Initialization in VHDL or Verilog Code
Additional RAMB18E5 and RAMB36E5 Primitive Design Considerations
Optional Output Registers
Output Register Reset
Independent Read and Write Port Width
RAMB18E5 and RAMB36E5 Port Mapping Design Rules
Byte-Wide Write Enable
Minimum Clock Pulse and Address/Enable Setup/Hold Time (Caution: Unstable Clocks)
Block RAM Applications
Block RAM RSTREG in Register Mode
Built-in Error Correction
ECC Modes
Top-Level View of the Block RAM ECC Architecture
Block RAM ECC Primitive
Block RAM ECC Port Descriptions
Block RAM ECC Attributes
ECC Modes of Operation
Standard ECC
ECC Encode Only
ECC Decode Only
Creating 8 Parity Bits for a 64-bit Word
Block RAM ECC VHDL and Verilog Templates
UltraRAM Resources
UltraRAM Key Features
UltraRAM Cascade
UltraRAM Error Correction Coding
Block RAM and UltraRAM Differences
Block RAM and UltraRAM Comparison
UltraRAM Primitives
UltraRAM Port Names and Description
No Cascade Ports
Cascade Ports
UltraRAM Port Signals
Clock – CLK
Power Gating Enable Input – SLEEP
Address Bus – ADDR_A, ADDR_B
Enable – EN_A and EN_B
Read/Write Select – RDB_WR_A and RDB_WR_B
Byte-Wide Write Enable – BWE_A, BWE_B
Data-In Buses – DIN_A, DIN_B
Inject Single and Double Bit Error Inputs – INJECT_SBITERR_A, INJECT_DBITERR_A, INJECT_SBITERR_B, INJECT_DBITERR_B
Register Enable for OREG Pipeline Stage – OREG_CE_A, OREG_CE_B
Register Enable for OREG_ECC Pipeline Stage – OREG_ECC_CE_A, OREG_ECC_CE_B
Reset – RST_A, RST_B
Data-Out Buses – DOUT_A, DOUT_B
Read Status Output – RDACCESS_A, RDACCESS_B
ECC Error Bit Output – SBITERR_A, DBITERR_A, SBITERR_B, DBITERR_B
Invertible Control Signal Pins
UltraRAM Attributes
Auto Sleep Latency – AUTO_SLEEP_LATENCY
Byte Write Enable Mode – BWE_MODE_[A|B]
Cascade Chain Order – CASCADE_ORDER_CTRL[A|B], CASCADE_ORDER_DATA_[A/B]
AVG_CONS_INACTIVE_CYCLES, MATRIX_ID, NUM_URAM_IN_MATRIX, and NUM_UNIQUE_SELF_ADDR_A|B Attributes
Set Enable Auto Sleep Mode – EN_AUTO_SLEEP_MODE
Enable ECC Write – EN_ECC_WR_[A/B]
Enable ECC Read – EN_ECC_RD_[A/B]
INIT_XX - UltraRAM Content Initialization
Optional Input Register Stage – IREG_PRE_[A|B]
Optional Output Register Stage – OREG_[A|B]
Optional ECC Output Register Stage – OREG_ECC_[A|B]
Optional Cascade Register Stage – REG_CAS_[A|B]
Reset Mode – RST_MODE_[A|B]
Self Address – SELF_ADDR_[A|B]
Self Mask Value – SELF_MASK_[A|B]
External CE Usage – USE_EXT_CE_[A|B]
Additional URAM288E5 Primitive Design Considerations
Optional Output Registers
Output Register Reset
Optional Sleep Mode
Minimum Clock Pulse and Address/Enable/Sleep Setup/Hold Time (Caution: Unstable Clock)
Dual Port SRAM Array Operations
Read Operation
Write Operation
Optional Input Registers
Optional Output Registers
RESET Operation
Byte Write Enable Function
Cascading UltraRAM and Matrix Configurations
Cascade User Attributes
Building a Matrix From Cascaded UltraRAMs
Address Bit Decoding
Built-in Error Detection and Correction
ECC Modes
ECC Modes of Operation
Standard ECC
Standard ECC Write
Standard ECC Read
ECC Encode Only
ECC Encode-Only Write
ECC Encode-Only Read
ECC Decode Only
Using ECC Decode Only to Inject Single-Bit Error
Using the ECC Decode Only to Inject Double-Bit Error
UltraRAM Timing Diagrams
Read/Write Waveforms With and Without Optional Pipeline Registers
Read/Write Waveforms With Reset – With and Without Optional Output Pipeline Registers
Read/Write Waveforms With External CE
Read From Matrix Waveforms With Reset
Sleep Waveforms
Auto Sleep Waveforms
Additional Resources and Legal Notices
Xilinx Resources
Documentation Navigator and Design Hubs
Please Read: Important Legal Notices
DIN[71:0] with double-bit error injected is written into the memory
array.
When the memory location is accessed, the corrupted data is read out
and a double-bit error is detected. The detected double-bit error can be two data
bit errors, or two parity bit errors, or one data bit error and one parity bit
error.
DBITERR lines up with the corresponding DOUT data.