Versal ACAP AI Engine Architecture Manual (AM009)

Document ID: AM009
Release Date: 2021-10-21
Revision: 1.2 English

Revision History
Overview
Introduction to Versal ACAP
Navigating Content by Design Process
AI Engine Array Features
AI Engine Array Overview
AI Engine Array Hierarchy
AI Engine Applications
Performance
Memory Error Handling
AI Engine Tile Architecture
Memory Mapped AXI4 Interconnect
AXI4-Stream Interconnect
AI Engine Tile Program Memory
AI Engine Interfaces
AI Engine Memory Module
AI Engine Data Movement Architecture
AI Engine to AI Engine Data Communication via Shared Memory
AI Engine Tile to AI Engine Tile Data Communication via Memory and DMA
AI Engine Tile to AI Engine Tile Data Communication via AXI4-Stream Interconnect
AI Engine to PL Data Communication via Shared Memory
AI Engine Debug
AI Engine Trace and Profiling
Trace
Profiling (Performance Counters)
AI Engine Events
AI Engine Array Interface Architecture
AI Engine Array Interface
Features of the AI Engine Array Interface
Array Interface Memory-Mapped AXI4 Interconnect
Array Interface AXI4-Stream Interconnect
AI Engine to Programmable Logic Interface
AI Engine to NoC Interface
Interrupt Handling
AI Engine Architecture
Functional Overview
Register Files
Instruction Fetch and Decode Unit
Load and Store Unit
Scalar Unit
Arithmetic Logic Unit, Scalar Functions, and Data Type Conversions
Vector Unit
Fixed-Point Vector Unit
Floating-Point Vector Unit
Register Move Functionality
AI Engine Configuration and Boot
AI Engine Array Configuration
AI Engine Boot Sequence
AI Engine Array Reconfiguration
Additional Resources and Legal Notices
Xilinx Resources
Documentation Navigator and Design Hubs
References
Please Read: Important Legal Notices

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