AI Engine Array Configuration

Versal Adaptive SoC AI Engine Architecture Manual (AM009)

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1.3 English

There are two top-level scenarios in the AI Engine array configuration: AI Engine array configuration from power-up and AI Engine array partial reconfiguration. The following figure shows a high-level view of the AI Engine array and configuration interface along with the registers to the PS and the platform management controller (PMC) through the NoC.

Figure 1. AI Engine Array Configuration using NoC and NPI

Any memory-mapped AXI4 master can configure any memory-mapped AXI4 register in the AI Engine array using the NoC (for example, the PS and PMC). The global registers (including PLL configuration, global reset, and security bits) in the array configuration interface tile can be programmed using the NPI interface because the global registers are mapped onto the NPI address space.

Configuration Time for AI Engine Array

AI Engine array configuration is done using a memory-mapped AXI4 over the NoC interface. NoC can support 128-bit transfers. Inside the AI Engine tile, the memory-mapped AXI4 has a 32-bit data transfer rate and can transfer from one to four 32-bit words in burst mode. An example of the configuration time for a typical design on the VCK190 board is shown in the following table.

Table 1. Example Configuration Time
Number of Tiles Program Size (MBytes) Time (ms)
315 9.7 22.727
400 17.7 35.067