AI Engine Array Features

Versal Adaptive SoC AI Engine Architecture Manual (AM009)

Document ID
AM009
Release Date
2023-08-18
Revision
1.3 English

Some Versal adaptive SoCs include the AI Engine array that consists of an array of AI Engine tiles and the AI Engine array interface consisting of the network on chip (NoC) and programmable logic (PL) tiles. The following lists the features of each.

AI Engine Tile Features

  • A separate building block, integrated into the silicon, outside the programmable logic (PL)
  • One AI Engine incorporates a high-performance very-long instruction word (VLIW) single-instruction multiple-data (SIMD) vector processor optimized for many applications including signal processing and machine learning applications among others
  • Eight banks of single-port data memory for a total of 32 KB
  • Streaming interconnect for deterministic throughput, high-speed data flow between AI Engines and/or the programmable logic in the Versal device
  • Direct memory access (DMA) in the AI Engine tile moves data from incoming stream(s) to local memory and from local memory to outgoing stream(s)
  • Configuration interconnect (through memory-mapped AXI4 interface) with a shared, transaction-based switched interconnect for access from external masters to internal AI Engine tile
  • Hardware synchronization primitives (for example, locks) provide synchronization of the AI Engine, between the AI Engine and the tile DMA, and between the AI Engine and an external master (through the memory-mapped AXI4 interface)
  • Debug, trace, and profile functionality

AI Engine Array Interface to NoC and PL Resources

  • Direct memory access (DMA) in the AI Engine array interface NoC tile manages incoming and outgoing memory-mapped and streams traffic into and out of the AI Engine array
  • Configuration and control interconnect functionality (through the memory-mapped AXI4 interface)
  • Streaming interconnect that leverages the AI Engine tile streaming interconnect functionality
  • AI Engine to programmable logic (PL) interface that provides asynchronous clock-domain crossing between the AI Engine clock and the PL clock
  • AI Engine to NoC interface logic to the NoC master unit (NMU) and NoC slave unit (NSU) components
  • Hardware synchronization primitives (for example, locks) leverage features from the AI Engine tile locks module
  • Debug, trace, and profile functionality that leverage all the features from the AI Engine tile