AI Engine Array Interface Architecture

Versal Adaptive SoC AI Engine Architecture Manual (AM009)

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1.3 English

The AI Engine is arranged in a 2D array as shown in the following figure. The AI Engine array interface provides the necessary functionality to interface with the rest of the device. The AI Engine array interface has three types of AI Engine interface tiles. There is a one-to-one correspondence of interface tiles for every column of the AI Engine array. The interface tiles form a row and move memory-mapped AXI4 and AXI4-Stream data horizontally (left and right) and also vertically up a AI Engine tile column. The AI Engine interface tiles are based on a modular architecture, but the final composition is device specific. Refer to the following figure for the internal hierarchy of the AI Engine array interface in the AI Engine array.

Figure 1. AI Engine Array Interface Hierarchy

The types of array interface tiles and the modules within them are described in this section.

  • AI Engine PL interface tile
    • PL module includes:
      • AXI4-Stream switch
      • Memory-mapped AXI4 switch
      • AI Engine to PL stream interface
      • Control, debug, and trace unit
  • AI Engine configuration interface tile (exactly one instance per AI Engine array)
    • PLL for AI Engine clock generation
    • Power-on-reset (POR) unit
    • Interrupt generation unit
    • Dynamic function exchange (DFx) logic
    • NoC peripheral interconnect (NPI) unit
    • AI Engine array global registers that control global features such as PLL/clock control, secure/non-secure behavior, interrupt controllers, global reset control, and DFx logic
  • AI Engine NoC interface tile
    • PL module (see previous description)
    • NoC module with interfaces to NMU and NSU includes:
      • Bi-directional NoC streaming interface
      • Array interface DMA