AI Engine Debug

Versal Adaptive SoC AI Engine Architecture Manual (AM009)

Document ID
Release Date
1.3 English

Debugging the AI Engine uses the memory-mapped AXI4 interface. All the major components in the AI Engine array are memory mapped.

  • Program memories
  • Data memories
  • AI Engine registers
  • DMA registers
  • Lock module registers
  • Stream switch registers
  • AI Engine break points registers
  • Events and performance counters registers

These memory-mapped registers can be read and/or written from any master that can produce memory-mapped AXI4 interface requests (PS, PL, and PMC). These requests come through the NoC to the AI Engine array interface, and then to the target tile in the array. The following figure shows a typical debugging setup involving a software development environment running on a host development system combined with its integrated debugger.

Figure 1. Overview of the AI Engine Debug Interface

The debugger connects to the platform management controller (PMC) on an AI Engine enabled Versal device either using a JTAG connection or the AMD high-speed debug port (HSDP) connection.