AI Engine Tile to AI Engine Tile Data Communication via Memory and DMA

Versal Adaptive SoC AI Engine Architecture Manual (AM009)

Document ID
AM009
Release Date
2023-08-18
Revision
1.3 English

The communication described in the previous section is inside an AI Engine tile or between two neighboring AI Engine tiles. For non-neighboring AI Engine tiles, a similar communication can be established using the DMA in the memory module associated with each AI Engine tile, as shown in the following figure. The synchronization of the ping-pong buffers in each memory module is carried out by the locks in a similar manner to the AI Engine to AI Engine Data Communication via Shared Memory section. The main differences are increased communication latency and memory resources.

Figure 1. Data Communication Between Two Non-neighboring AI Engine Tiles