AI Engine to AI Engine Data Communication via Shared Memory

Versal Adaptive SoC AI Engine Architecture Manual (AM009)

Document ID
AM009
Release Date
2023-08-18
Revision
1.3 English

AI Engine to AI Engine Data Communication via Shared Memory

In the case where multiple kernels fit in a single AI Engine, communications between two consecutive kernels can be established using a common buffer in the shared memory. For cases where the kernels are in separate but neighboring AI Engine, the communication is through the shared memory module. The processing of data movement can be through a simple pipeline or multiple parallel pipe stages (see the following figure). Communication between the two AI Engines can use ping and pong buffers (not shown in the figure) on separate memory banks to avoid access conflicts. The synchronization is done through locks. DMA and AXI4-Stream interconnect are not needed for this type of communication.

The following figures show the data communication between the AI Engine tiles. They are a logical representation of the AI Engine tiles and shared memory modules.

Figure 1. AI Engine to AI Engine Data Communication via Shared Memory