Features of the AI Engine Array Interface

Versal Adaptive SoC AI Engine Architecture Manual (AM009)

Document ID
Release Date
1.3 English
Memory Mapped AXI4 Interconnect
Provides functionality to transfer the incoming memory-mapped AXI4 requests from the NoC to inside the AI Engine array.
AXI4-Stream Interconnect
Leverages the AI Engine tile streaming interconnect functionality.
AI Engine to PL Interface
The AI Engine PL modules directly communicate with the PL. Asynchronous FIFOs are provided to handle clock domain crossing.
AI Engine to NoC Interface
The AI Engine to NoC module handles the conversion of 128-bit NoC streams into 32-bit AI Engine streams (and vice versa). It provides the interface logic to the NoC components (NMU and NSU). Level shifting is performed because the NMU and NSU are in a different power domain from the AI Engine.
Hardware Locks
Leverages the corresponding unit in the AI Engine tile and is accessible from the AI Engine array interface or an external memory-mapped AXI4 master, the module is used to synchronize the array interface to DMA transfer to/from external memory.
Debug, Trace, and Profile
Leverages all the features from the AI Engine tile for local event debugging, tracing, and profiling.