Memory Mapped AXI4 Interconnect

Versal Adaptive SoC AI Engine Architecture Manual (AM009)

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1.3 English

Each AI Engine tile contains a memory-mapped AXI4 interconnect for use by external blocks to write to or read from any of the registers or memories in the AI Engine tile. The memory-mapped AXI4 interconnect inside the AI Engine array can be driven from outside of the AI Engine array by any AXI4 master that can connect to the network on chip (NoC). All internal resources in an AI Engine tile including memory, and all registers in an AI Engine and AI Engine memory module, are mapped onto a memory-mapped AXI4 interface.

Each AI Engine tile has a memory-mapped AXI4 switch that will accept all memory-mapped AXI4 accesses from the south direction. If the address is for the tile, access occurs. Otherwise, the access is passed to the next tile in the north direction.

The following figure shows the addressing scheme of memory-mapped AXI4 in the AI Engine tile. The lower 18 bits represent the tile address range of 0x00000 to 0x3FFFF, followed by five bits that represent the row location and seven bits that represent the column location.

Figure 1. AI Engine Memory-Mapped AXI4 Interface Addresses

The AI Engine internal memory-mapped AXI4 interconnect is a subset of the full memory-mapped AXI4 protocol, with the following limitations.

  • No write data before write address
  • Only one WSTRB signal for the write data
  • Only burst of one to four, 32-bit words
  • 32-bit fixed size